1. Field of the Invention
The present invention relates to a termination structure of a power semiconductor device and a manufacturing method thereof, and more particularly, to a termination structure of a power semiconductor device having a trench and a manufacturing method thereof.
2. Description of the Prior Art
Power semiconductor devices are typical semiconductor devices in power management applications, such as a switching power supply, a power control IC of a computer system or peripherals, a power supply of a backlight, motor controller, etc. Power semiconductor devices can include various kinds of transistors, such as an insulated gate bipolar transistor (IGBT) and a metal-oxide-semiconductor field effect transistor (MOSFET).
Because the power semiconductor device is designed to tolerate high voltage, an active device of the power semiconductor device usually is provided with high current. In order to prevent the semiconductor device from being broken down or having channeling effect with other devices, the power semiconductor device according to the prior art usually disposes a termination structure in a peripheral region surrounding the active device to avoid a voltage break down phenomenon and isolate the influence of the active device on the outside devices. The popular termination structure in the prior art is local oxidation of silicon (LOCOS), field plate or guard ring.
Refer to FIG. 1, which is a schematic diagram illustrating a power semiconductor device utilizing a field oxide layer to be a termination structure according to the prior art. As shown in FIG. 1, the semiconductor substrate 10 includes an N-type substrate 12 and an N-type epitaxial layer 14, and the semiconductor substrate 10 has an active region 16 and a peripheral region 18. The N-type epitaxial layer 14 in the active region 16 has a plurality of trenches 20, and the gate oxide layer 22 and the polysilicon layer 24 are respectively formed in each trench 20. In addition, the field oxide (FOX) layer 26 is formed on the N-type epitaxial layer 14 in the peripheral region 18, and a P-type doped region 28 is disposed in the N-type epitaxial layer 14 under the field oxide layer 26 for reduce the breakdown voltage. An anode 30 formed on the N-type epitaxial layer 14 extends onto the field oxide layer 26 to change a depletion region between the P-type doped region 28 and the N-type epitaxial layer 14, so that high electric field in the active region 16 can be reduced.
Refer to FIG. 2, which is a schematic diagram illustrating a guard ring structure according to the prior art. As shown in FIG. 2, a plurality of P-type doped regions 52, each of which is a ring structure, are disposed in the N-type epitaxial layer 50, and surround the outside of the active region in sequence. The power semiconductor device of the prior art can utilize the depletion region formed by each P-type doped region 52 and the N-type epitaxial layer 50 to reduce the strength of the electric field.
However, the termination structure of the prior art in size generally requires a width of over 20 micrometers to efficiently reduce the high electric field, so that the size of the power semiconductor device is limited by the width of the termination structure with shrinking the size of the devices. Furthermore, the process of forming the termination structure of the prior art require extra step to form P-type doped region in the N-type epitaxial layer for reduce the high electric field of the power semiconductor device through the depletion region, but the process of fabricating the termination structure of the prior art need a photomask to perform a P-type ion implantation process, so that the manufacturing cost cannot be further reduced.
Accordingly, it is still needed for a novel termination structure of a power semiconductor device and a novel manufacturing method thereof to shrink the termination structure of the power semiconductor device and reduce the number of the photomasks.